The trend in semiconductor technology to double the functional complexity of its products every 18 months (Moore's "law"), which is still valid today after having dominated the industry for the last three decades, has several implicit consequences. First, the cost per functional unit should drop with each generation of complexity so that the cost of the product with its doubled functionality would increase only slightly. Second, the higher product complexity should largely be achieved by shrinking the feature sizes of the chip components while holding the package dimensions constant; preferably, even the packages should shrink. Third, the increased functional complexity should be paralleled by an equivalent increase in reliability of the product. And fourth, but not least, the best financial profit rewards were held out for the ones who were ahead in the marketplace in reaching the complexity goal together with offering the most flexible products for application.
For semiconductor memory devices, historically the time span of at least three years has been needed between two generations of memory families. The new generation offers a four times larger memory capacity compared to the preceding generation. Again, shrinking circuit feature sizes and more complex memory hierarchies have been the prerequisite of the new product generation--at high development cost for chip design and fabrication processes, coupled with very expensive investment in costly new manufacturing equipment.
A number of technical advances have recently been achieved in an effort to obtain an advantage in this competitive marketplace. Within the semiconductor memory product families, one of the most promising concepts for shrinking the package outline and thus consuming less area when the device is mounted onto the circuit board, has been the so-called "board-on-chip" design replacing the traditional metallic leadframe. Patent application Ser. No. 9702348-5 entitled "Board on Chip--Ball Grid Array Chip Size Package" has been filed by Texas Instruments in Singapore on Jul. 02, 1997. This patent application for memory products successfully approaches the problem of reducing the area requirement by replacing the traditional leaded package design with a solder ball concept. In addition, it offers a reduction in the height requirement by replacing the leadframe-on-chip assembly with a thinner and more flexible board-on-chip design. Using the new concept, a high-density integrated circuit package has been described in patent application Ser. No. 9703963-0 entitled "High Density 3-Dimensional Stacked Ball Grid Array Integrated Circuit Module", filed by Texas Instruments in Singapore on Nov. 6, 1997. A new modification using thin board-on-chip devices entitled "Thin Board-on-Chip Integrated Circuit Unit" has been submitted by Texas Instruments in Singapore, also in 1997.
It is frustrating, though, that in spite of all this progress so much time and money has to be spent continuously for testing and burning-in each new package and each new device. Required are design and acquisition of dedicated burn-in and test sockets for each different input/output count and each different package configuration; dedicated sockets, boards, trays, tubes and handlers; lack of standardization of equipment and procedures for testing and burn-in; and limited comparison of accumulated data. Due to ever modified package outlines, testing and burn-in remain dedicated fabrication steps with no interchangeablity. Consequently, a need has arisen for package designs and methods of device fabrication that provide simple, low-cost designs for a universal fanout package concept with a configuration suitable for an entire device family. Preferably, these improvements should be accomplished using the installed equipment base so that no investment in new burn-in and testing facilities is needed.